(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form a composite insulator spacer on the sides of a metal oxide semiconductor field effect transistor (MOSFET), gate structure.
(2) Description of Prior Art
The emergence of micro-miniaturization, or the ability to fabricate semiconductor devices with sub-micron features, has allowed the performance of the sub-Micron devices to be increased while the processing costs for these same devices has been reduced. Reduction in performance degrading parasitic junction capacitance, in addition to the ability to obtain a greater amount of smaller semiconductor chips comprised with sub-micron features, from a specific size starting substrate, has allowed the desired performance and costs enhancements to be realized. However as device features shrink specific phenomena not present for devices comprised with larger features can arise. For example during dry etching procedures a micro-loading phenomena, or the phenomena of increased etch rates in areas of densely packed features, can adversely influence yield and reliability of devices formed with sub-micron features. For example the definition of insulator spacers formed on the sides of gate structures, can be influenced by the spacing between gate structures. The etch rate for the anisotropic reactive ion etch (RIE), procedure used for insulator spacer definition can be greater in an area of the semiconductor chip in which the spacing between gate structures is less when compared to an area of the semiconductor chip in which the spacing between gate structures is greater. While insulator spacer definition is still continuing in less dense regions the enhanced etch rate of insulator in the densely packed regions can result in insulator spacing thinning or attack of the semiconductor surface located between the densely packed gate structures. This deleterious phenomena can result in yield and performance degradation of a semiconductor device, such as a dynamic random access memory (DRAM), device, in which the device refresh time (TREF), can be degraded if the semiconductor is attacked during insulator spacer definition.
This invention will describe a novel composite insulator spacer, and the method used to define the novel composite spacer on the sides of MOSFET gate structures. The present invention will feature spacer materials and etch chemistries which allow increased etch rate selectivity to be achieved, thus reducing the risk of enhanced etching in tightly packed spaces, thus preserving the integrity of the device. Prior art such as Yen et al, in U.S. Pat. No. 6,376,384 B1, Ikegami, in U.S. Pat. No. 6,355,572 B1, Matsumoto et al, in U.S. Pat. No. 6,346,482 B2, and Coronel et al, in U.S. Pat. No. 6,342,452 B1, describe methods of etching dielectric layers. However none of the above prior art describe the novel features of the present invention in which the combination of composite insulator materials and etch chemistries are used to define composite insulator spacers on the sides of either tightly packed or less densely packed gate structures.
It is an object of this invention to form a composite insulator spacer on the sides of a metal oxide semiconductor field effect (MOSFET), gate structure.
It is another object of this invention to employ a selective dry etch procedure for the composite insulator spacer in which the material chosen for the underlying insulator component of the composite insulator spacer features a lower etch rate than the material chosen for the overlying insulator component of the composite insulator spacer, using a first dry etch chemistry.
It is still another object of this invention to employ a selective dry etch procedure for the composite insulator spacer in which the material chosen for the underlying insulator component of the composite insulator spacer features a higher etch rate than the etch rate of the semiconductor substrate, using a second dry etch chemistry.
In accordance with the present invention a method of defining a composite insulator spacer on the sides of a gate structure, using a selective dry etch procedure with reduced micro-loading phenomena and thus less risk of semiconductor damage, is described. After definition of a conductive gate structure on an underlying gate insulator layer, a thin layer of undoped silicate glass (USG), layer is deposited. A silicon oxide layer, obtained using tetraethylorthosilicate (TEOS), as a source is deposited on the USG layer. A first phase of a dry etch procedure used to define a composite insulator spacer on the sides of the conductive gate structure, is performed using a first etch chemistry featuring a high etch rate selectivity of TEOS silicon oxide to underlying USG. At the appearance of the USG layer a second phase of the dry etch procedure, employing a second etch chemistry is initiated, featuring a high etch rate selectivity of USG insulator to underlying silicon, allowing the second phase of the dry etch procedure to terminate at the appearance of the surface of the semiconductor substrate. The selective dry etch procedure reduces the risk of semiconductor damage, even in narrow spaces located between conductive gate structures.